Also known as: RISC-V, RISCV
RISC-V is an open, royalty-free RISC instruction set architecture that anyone can implement without a license fee.1
Overview
Where x86 and ARM are owned and licensed, RISC-V is a free and open standard stewarded by RISC-V International. It is built as a small mandatory base integer instruction set plus optional extensions (for multiplication, floating point, vectors, and more), so a designer picks only what a chip needs. This modular, open model lets universities, startups, and large vendors build compatible processors from tiny microcontrollers up to application cores without royalties.
Where it fits
RISC-V’s appeal is freedom from licensing and the ability to customize the ISA, which has made it popular in research, education, and embedded designs, with broader adoption growing. It competes with ARM in efficiency-focused niches and offers an open alternative to both incumbents. For a toolchain like GopherTrunk’s, supporting a new ISA is mostly a matter of the compiler gaining a target — the open ISA lowers the barrier to that happening.