Phase-locked loop (PLL)

Also known as: PLL

A phase-locked loop (PLL) is a feedback control system that drives an internal oscillator to match the phase — and therefore the frequency — of a reference input.¹ It compares the input phase against the oscillator’s phase, filters the error, and steers the oscillator to null that error, producing a local copy that stays synchronized with the incoming signal. PLLs are the backbone of carrier recovery, symbol-clock recovery, and frequency synthesis across nearly all radio and clocking systems.

A PLL nulls the phase difference between a reference and its own oscillator: the phase detector's error is smoothed by the loop filter and fed back to tune the VCO/NCO.

How it works

Three blocks in a loop:

Phase detector — outputs a signal proportional to the phase difference between the input and the oscillator (a multiplier, an XOR, or a phase-frequency detector, depending on the design).
Loop filter — a low-pass (usually proportional-plus-integral) filter that removes detector noise and sets the loop’s dynamics. Its integrator lets the loop hold a nonzero frequency offset with zero steady-state phase error.
Controlled oscillator — a VCO in analog hardware or, in DSP, a numerically-controlled oscillator whose instantaneous phase is advanced by the filtered error.

When the error is nonzero the loop nudges the oscillator until the phases agree; at that point it is locked and the oscillator frequency equals the input frequency. Because phase is the integral of frequency, locking phase automatically locks frequency.

Loop order and bandwidth

Two knobs dominate PLL behaviour:

Order/type. A first-order loop is simple but leaves a static phase offset under a frequency error. A second-order type-II loop (one extra integrator in the filter) tracks a constant frequency offset with zero phase error and is the workhorse for carrier and clock recovery. Its dynamics are set by a natural frequency and a damping factor (≈0.707 is a common critically-damped choice).
Loop bandwidth. Wide bandwidth locks fast and tracks jitter/Doppler but lets in more noise; narrow bandwidth is cleaner but slower to acquire and has a smaller pull-in range. Many receivers open the bandwidth to acquire, then narrow it to track — or precede the PLL with a frequency-locked loop or AFC to remove coarse offset first, since a PLL alone has a limited frequency pull-in range.

Variants

Costas loop — a PLL variant whose phase detector is built to recover a suppressed carrier from a modulated signal, so it can lock to PSK where there is no discrete carrier tone. See costas-loop.
Frequency synthesizer — a PLL with a frequency divider in the feedback path multiplies a stable reference up to a tunable output, the basis of the local oscillators in nearly every radio.
All-digital PLL — the entire loop implemented in DSP around an NCO, the norm in software radio.

Relevance to SDR

PLLs (and their Costas cousin) recover the carrier for phase-modulated modes, discipline sample clocks, and — in hardware — synthesize the tuning frequency of SDR front-ends. In a trunking decoder a carrier-tracking loop keeps a constellation from rotating so symbol decisions stay valid. GopherTrunk uses digital carrier/timing feedback loops in its C4FM and π-4-DQPSK demodulation chains; the PLL is the general pattern those loops instantiate.

Sources

Phase-locked loop — Wikipedia, on the phase-detector/loop-filter/oscillator feedback structure, loop order, and lock behaviour. ↩