Hardware acceleration is the practice of offloading a task from the general-purpose CPU onto specialized hardware built to do it faster, more efficiently, or both.1
Overview
A CPU is a generalist: it can run any code, but it pays for that flexibility in speed and power. When a task is performed constantly and has a regular structure — graphics, video encoding, neural-network math, signal processing — it is often worth building hardware that does only that. Accelerators span a spectrum: the programmable GPU and vector units, the reconfigurable FPGA, and the fixed-function ASIC, with flexibility falling and efficiency rising along the way.
The gains come from two sources: doing many operations at once (parallelism) and doing each with circuitry shaped exactly to the task rather than a general instruction pipeline. A dedicated video encoder or crypto block can beat a CPU by orders of magnitude in both speed and energy per operation — but it can do nothing else, and it cannot be changed once fabricated.
How it works
The engineering choice is how much to freeze in silicon. The more a design commits to one task, the faster and leaner it runs it, and the less it can do anything else:
| Accelerator | Programmability | Best at | Cost |
|---|---|---|---|
| CPU | Fully general | Anything, sequentially | Slowest per watt |
| GPU | Software kernels | Data-parallel math | Transfer overhead |
| FPGA | Reconfigurable logic | Custom pipelines, low latency | Hard to develop |
| ASIC | Fixed at fabrication | One job, at scale | No changes, high NRE |
Because offloading adds data-transfer and coordination overhead, it pays only when the accelerated portion is both large and regular — Amdahl’s law limits how much a fast accelerator can help if most of the runtime is still ordinary CPU code.
Where it fits
The engineering question is always what to offload: moving work to an accelerator adds complexity and data-transfer overhead, so it pays only when the speedup is large or the CPU genuinely cannot keep up. This is a live trade-off in software-defined radio. GopherTrunk does its DSP and protocol decoding in software on the CPU, deliberately keeping the radio a simple front end and leaning on CPU vector units for the per-sample math; an FPGA doing channelization in hardware would accelerate wideband, many-channel capture, at the cost of flexibility and a much harder development path.
Sources
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Hardware acceleration — Wikipedia, on offloading tasks from the CPU to specialized hardware and the flexibility-versus-efficiency spectrum. ↩