Field Guide · concept

Also known as: Array processor

A vector processor is a processor designed to apply a single instruction to a whole array of data elements at once, rather than one element per instruction.1

Scalar · one add per instruction a0 + b0 = c0 ← instruction 1 ... then a1+b1, a2+b2, a3+b3 — four separate instructions Vector / SIMD · one add, four lanes a0 a1 a2 a3 + b0 b1 b2 b3 = c0 c1 c2 c3 ← one instruction
A scalar processor adds one pair of numbers per instruction, so a four-element array costs four instructions; a vector (SIMD) unit adds all four lanes with a single instruction, amortizing the overhead across the whole array.

Overview

The model is SIMD — single instruction, multiple data. Where a scalar processor adds two numbers per add instruction, a vector unit adds two arrays of numbers in one go, amortizing instruction overhead and keeping wide arithmetic pipelines full. The idea powered the early Cray supercomputers and survives today as the SIMD extensions built into ordinary CPUs (Intel’s SSE/AVX, ARM’s NEON) and, taken to an extreme, in the thousands-of-lanes design of the GPU.

The win is twofold: fewer instructions are fetched and decoded for the same work, and the hardware can lay out identical arithmetic units side by side as lanes that all fire together. The limit is that every lane must do the same operation in lock-step, so vector code favours long, regular arrays with no per-element branching — the further the data strays from that shape, the less the vector unit helps.

Anatomy

A vector unit is defined by how wide it is and how it handles data that does not fill its lanes cleanly:

Property Scalar Vector / SIMD
Elements per instruction One Many (a full register width)
Instruction overhead Per element Amortized over the lanes
Best-case shape Any Long, regular arrays
Branch handling Free Costly (predication or masks)
Examples Plain add AVX, NEON, GPU warps

Because all lanes share one instruction stream, a vector unit spends far less silicon on control and far more on arithmetic than a scalar core — the same bargain a GPU takes to its extreme.

Where it fits

Vector processing is the foundation of GPGPU and of most numeric hardware acceleration: any workload that does the same math across long, regular arrays benefits. Digital signal processing is a prime example — a FIR digital filter or an FFT multiplies and sums across streams of samples, exactly the data-parallel shape SIMD exploits. GopherTrunk’s per-sample DSP on the CPU leans on these vector units to keep up with high sample rates, processing many IQ samples per instruction rather than one at a time.

Sources

  1. Vector processor — Wikipedia, on SIMD/array processor architectures, lanes, and the scalar-versus-vector distinction. ↩

See also