SoC vs discrete is the design trade-off between integrating the processor and its accelerators onto a single system-on-a-chip versus using separate, dedicated chips wired together on a board.1
Overview
An integrated approach puts the CPU, GPU, NPU, memory controller, and I/O on one die that shares a single pool of memory. A discrete approach gives an accelerator its own chip and its own high-bandwidth memory, connected over a bus such as PCI Express. Integration shortens the distance data has to travel, cutting power and latency; separation lets each part be made as large and fast as its own package allows.
Shared memory is the pivotal difference. On an SoC the CPU and its accelerators read the same RAM, so passing data between them can be nearly free — no copy across a bus. A discrete accelerator has its own dedicated memory that is faster and larger than what an SoC can share, but every hand-off means copying data across the interconnect, which costs both time and energy.
Trade-offs
The two designs optimise for opposite ends of the power-and-performance curve, and the right pick follows the device it lives in:
| Aspect | SoC (integrated) | Discrete (separate) |
|---|---|---|
| Memory | Shared pool | Own dedicated memory |
| Power & size | Low, compact | High, bulky |
| Peak performance | Limited by die area | As large as its package |
| Data movement | Nearly free on-die | Copy across the bus |
| Upgradability | Fixed | Swap the card |
| Typical home | Phones, SBCs, edge | Data centers, gaming PCs |
Where it fits
The SoC wins on power, physical size, and cost — which is why phones, single-board computers, and edge devices use integrated accelerators. The discrete part wins on peak performance and upgradability, which is why data-center training rigs and gaming PCs bolt on standalone GPUs with dedicated memory. The choice mirrors the broader hardware-acceleration question of where compute should live. For a GopherTrunk capture node, an integrated SoC board by the antenna is the natural pick: low power and small, with the radio front end doing the heavy RF work, while a rack-mounted decode server can justify a discrete GPU for many-channel processing.
Sources
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System on a chip — Wikipedia, on integrating components onto a single chip versus discrete designs and shared versus dedicated memory. ↩