Also known as: CORDIC, coordinate rotation digital computer, Volder's algorithm
CORDIC (COordinate Rotation DIgital Computer) computes trigonometric and related
functions — sine, cosine, atan2, vector magnitude and phase — using only bit-shifts,
additions, and a small lookup table, with no hardware multiplier.12 It works
by rotating a 2-D vector toward a target angle (or toward the x-axis) in a fixed sequence of
ever-smaller steps whose tangents are exact powers of two, so each rotation collapses to a
shift-and-add. That makes it the natural choice for FPGA
and fixed-point hardware where multipliers are scarce but shifts are free.
How it works
A rotation by angle θ can be decomposed into a series of micro-rotations by fixed angles
αᵢ = atan(2⁻ⁱ). Rotating by such an angle requires multiplying by tan(αᵢ) = 2⁻ⁱ, which is
simply a right-shift by i bits. At each iteration CORDIC decides the sign of the next
micro-rotation and updates the vector:
xᵢ₊₁ = xᵢ ∓ (yᵢ >> i), yᵢ₊₁ = yᵢ ± (xᵢ >> i),
while accumulating the angle from a tiny stored table of the αᵢ. Each step gains roughly one
bit of accuracy, so n iterations give ~n bits of precision. A fixed gain of about 1.647
(the product of the per-step scale factors) is corrected once by a constant. CORDIC runs in
two dual modes:
- Rotation mode drives the residual angle to zero: feed in θ and a unit vector, and the
final
(x, y)arecos θandsin θ. This is how you synthesise a sinusoid. - Vectoring mode drives the residual y to zero: feed in a vector
(I, Q), and the accumulated angle isatan2(Q, I)while the finalxis the magnitude√(I²+Q²). This is how you get phase and amplitude from a complex sample.
Because every step is a shift and an add, CORDIC pipelines beautifully in hardware — one stage
per iteration — delivering a new result every clock cycle. Hyperbolic and linear variants
extend the same idea to sinh/cosh, exponentials, logarithms, multiply, and divide.
In practice
CORDIC trades multipliers for latency: it needs one iteration per bit rather than a single multiply, so on a modern CPU with fast hardware multipliers a table or polynomial is usually quicker. Its home turf is fixed-point hardware — FPGAs, ASICs, and small DSP cores — where a multiplier is expensive silicon and a shift is nearly free, and where the fully-pipelined, constant-throughput structure is exactly what a streaming signal path wants.
Relevance to SDR
CORDIC is pervasive in radio hardware. A numerically-controlled oscillator in an FPGA commonly generates its quadrature sine/cosine with a rotation-mode CORDIC instead of a large sine ROM, and the digital down-converters and up-converters inside SDR chips and transceivers use it to mix signals to and from baseband. In vectoring mode it is the standard way to build an FM discriminator — the instantaneous phase of successive I/Q samples, differenced, is the frequency — and to compute the magnitude/phase needed for AM detection, quadrature demodulation, and constellation angle measurement. Its multiplier-free nature is why it shows up in the front ends of RTL-SDR-class silicon, Airspy/HackRF-adjacent FPGA designs, and countless embedded radios.
GopherTrunk runs on general-purpose CPUs, so its own down-conversion and demodulation use ordinary floating-point trig and complex arithmetic rather than a CORDIC core; the algorithm’s importance to GT’s world is upstream, in the device hardware and FPGA front ends that deliver clean I/Q for GT to decode. Knowing CORDIC explains how those multiplier-light front ends generate their oscillators and discriminators.
Sources
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CORDIC — Wikipedia, on the shift-add rotation algorithm, its rotation and vectoring modes, and hardware use. ↩
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The CORDIC Trigonometric Computing Technique — J. E. Volder, IRE Transactions on Electronic Computers (1959), the original description of the algorithm. ↩